X86-64

Basic Program Execution Registers

IA-32 16 registers

General-Purpose Regsiters

String instructions use the contents of the ECX, ESI, and EDI registers as operands. When using a segmented memory model, some instructions assume that pointers in certain registers are relative to specific segments.

Special uses:

• EAX — Accumulator for operands and results data.

• EBX — Pointer to data in the DS segment.

• ECX — Counter for string and loop operations.

• EDX — I/O pointer.

• ESI — Pointer to data in the segment pointed to by the DS register; source pointer for string operations.

• EDI — Pointer to data (or destination) in the segment pointed to by the ES register; destination pointer for string operations.

• ESP — Stack pointer (in the SS segment).

• EBP — Pointer to data on the stack (in the SS segment).

General-Purpose Registers in 64-Bit Mode

In 64-bit mode, there are limitations on accessing byte registers. An instruction cannot reference legacy high-bytes (for example: AH, BH, CH, DH) and one of the new byte registers at the same time (for example: the low byte of the RAX register which would be referred to as AL).

However, instructions may reference legacy low-bytes (for example: AL, BL, CL, or DL) and new byte registers at the same time (for example: the low byte of the R8 register, or RBP).

The architecture enforces this limitation by changing high-byte references (AH, BH, CH, DH) to low byte references (BPL, SPL, DIL, SIL: the low 8 bits for RBP, RSP, RDI, and RSI) for instructions using a REX prefix.

• 64-bit operands generate a 64-bit result in the destination general-purpose register.

• 32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in the destination general-purpose register.

• 8-bit and 16-bit operands generate an 8-bit or 16-bit result. The upper 56 bits or 48 bits (respectively) of the destination general-purpose register are not modified by the operation. If the result of an 8-bit or 16-bit operation is intended for 64-bit address calculation, explicitly sign-extend the register to the full 64-bits.

In 32-bit modes, the upper 32 bits of 64-bit general-purpose registers are not defined. Therefore, when transitioning from 64-bit mode to a 32-bit mode (such as protected mode or compatibility mode), the upper 32 bits of any general-purpose register will not retain their previous values.

Control and Status Registers

• Program Counter (PC)

  Contains the address of an instruction to be fetched

• Instruction Register (IR) Contains the instruction most recently fetched.

• Program Status Word (PSW)

  condition code bits

  Interrupt enable/disable

  Supervisor/user(or kernel/user)mode